1. Field of the Invention
The present invention relates to a semiconductor device such as a MOS FET and, particularly, to a semiconductor device for switching.
2. Description of Related Art
MOS FETs (metal oxide semiconductor field effect transistors) include a so-called trench-type MOS FET, which has a trench formed in a surface of a silicon substrate thereof. The MOS FET includes a plurality of cells each having a source region, a drain region, a channel region provided between the source region and the drain region, and a gate electrode. In each of the cells of the trench-type MOS FET, the source and drain regions and the gate electrode are disposed so that a channel is formed alongside an interior side surface of the trench.
This allows for microminiaturization of the cells (devices), so that the number of cells per unit area can be increased by densely arranging the microminiaturized cells. Thus, a channel formation area per unit area is increased, so that the ON-resistance is reduced.
FIG. 4 is a schematic sectional view of a conventional MOS FET 51 in production. An N−-type epitaxial layer 52 is provided in a surface of a silicon substrate. A P−-region 53 is provided on the epitaxial layer 52. A trench 54 is provided as extending through the P−-region 53 to the middle of the thickness of the epitaxial layer 52. N+-type source regions 55 are respectively provided on edges of the trench 54. A gate oxide film 57 of silicon oxide is provided on an interior wall of the trench 54.
A gate electrode 56 of polysilicon imparted with electrical conductivity by implantation of an impurity is provided in the trench 54. An electrode not shown is provided on the silicon substrate. When a predetermined voltage is applied between the electrode and the source regions 55 and the gate electrode 56 is kept at a predetermined potential, an electric current (drain current) flows between the source regions 55 and the epitaxial layer 52. The drain current flows alongside the gate oxide film 57 through portions of the P−-region 53 adjacent to the gate oxide film 57.
The surface of the silicon substrate has a (100) plane orientation. Therefore, the surface of the epitaxial layer 52 (parallel to the surface of the silicon substrate) also has a (100) plane orientation. The P−-regions 53 and the source regions 55 are each formed by implanting an impurity into the surface of the N−-type epitaxial layer 52 and, hence, have the same crystallographic orientation as the silicon substrate and the epitaxial layer 52.
Interior side surfaces 54s of the trench 54 each have a (100) plane orientation. Therefore, the drain current flows along planes each having a (100) plane orientation (hereinafter referred to as “(100) planes”) in the P−-regions 53. Thus, the field effect efficiently occurs in the silicon surface to form channels, so that the ON-resistance is reduced.
MOS FETs having such a construction are disclosed in Japanese Unexamined Patent Publications No. 10-154809 (1998) and No. 10-154810 (1998).
With a recent trend toward thickness reduction of the gate oxide film 57, however, the capacitance of the gate oxide film 57 (hereinafter referred to as “gate capacitance Qg”) tends to be increased. This deteriorates the switching characteristic of the MOS FET 51, thereby increasing power consumption.
If the thickness of the gate oxide film 57 is increased, it is possible to reduce the gate capacitance Qg to improve the switching characteristic of the MOS FET 51. However, the width of an inversion layer (channel) formed when the gate electrode 56 is kept at a predetermined potential is reduced, as the thickness of the gate oxide film 57 is increased (in the extreme case, no inversion layer is formed). Therefore, the increase of the thickness of the gate oxide film 57 increases the ON-resistance. That is, it is impossible to simultaneously achieve the reduction of the ON-resistance and the improvement of the switching characteristic in the conventional MOS FET 51.
The ON-resistance can be reduced by reducing the thickness of portions of the gate oxide film 57 adjoining the P−-regions 53. Therefore, the reduction of the ON-resistance and the improvement of the switching characteristic may simultaneously be achieved by reducing the thickness of the portions of the gate oxide film 57 adjoining the P−-regions 53, and increasing the thickness of the other portion of the gate oxide film 57. However, such a structure cannot be realized for the following reason.
Since the trench 54 is formed perpendicularly to the silicon substrate, a bottom surface 54b of the trench 54 mainly has a (100) plane orientation like the interior side surface 54s. The formation of the gate oxide film 57 is typically achieved by thermally oxidizing the interior wall of the trench 54, so that the interior surfaces having the same plane orientation are oxidized to the same thickness. Therefore, the portions of the gate oxide film 57 on the interior side surfaces 54s and a portion of the gate oxide film 57 on the bottom surface 54b have substantially the same thickness, which is equal to a thickness d(100) resulting from the thermal oxidation of the (100) plane of the crystalline silicon. Therefore, the capacitance CGS per unit area of the portions of the gate oxide film 57 on the interior side surfaces 54s is virtually equal to the capacitance CGD per unit area of the portion of the gate oxide film 57 on the bottom surface 54b. 
Therefore, the increase of the thickness of the gate oxide film 57 reduces the gate capacitance Qg to improve the switching characteristic, but increases the ON-resistance. Conversely, the reduction of the thickness of the gate oxide film 57 reduces the ON-resistance, but increases the gate capacitance Qg to deteriorate the switching characteristic.
It is also conceivable to allow the gate oxide film 57 to have different thicknesses on the interior side surfaces 54s and on the bottom surface 54b by allowing the bottom surface 54b to have a plane orientation different from the plane orientation of the interior side surfaces 54s. More specifically, it is possible to achieve the aforesaid thickness relation of the gate oxide film 57 by allowing the interior side surfaces 54s to have a (100) plane orientation and allowing the bottom surface 54b to have a specific plane orientation different from the (100) plane orientation.
However, the trench 54 has not only the interior side surfaces 54s (hereinafter referred to as “first interior side surfaces”) shown in FIG. 4 but also interior side surfaces (hereinafter referred to as “second interior side surfaces”) which are oriented differently from the first interior side surfaces 54s (e.g., perpendicularly to the first interior side surfaces 54s). If the bottom surface 54b has a plane orientation different from the (100) plane orientation, the second interior side surfaces also have the plane orientation different from the (100) plane orientation. Since the source regions 55 are provided along all the edges of the trench 54, channels are formed in portions of the P−-regions 53 alongside the second interior side surfaces.
Where the gate oxide film 57 is formed under the same conditions, a charge density (interfacial charge density) Qss per unit area in an interface between the gate oxide film 57 and the surface having the plane orientation different from the (100) plane orientation tends to be greater than an interfacial charge density Qss in an interface between the gate oxide film 57 and the surface having the (100) plane orientation. If the channel was formed alongside the surface having a greater interfacial charge density Qss in the channel region, the operation reliability of the semiconductor device would be deteriorated due to greater fluctuations in gate threshold voltage.